(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a manufacturing method thereof.
(b) Description of Related Art
A flat panel display such as a liquid crystal display (LCD) and an organic light emitting display (OLED) includes a display panel including a plurality of pixel electrodes, a plurality of thin film transistors (TFTs) connected thereto, and a plurality of signal lines connected to the TFTs, a plurality of drivers for driving the display panel, and a controller for controlling the drivers.
The signal lines include gate lines for transmitting gate signals from the drivers to the TFTs and data lines for transmitting data signals from the drivers to the TFTs.
A TFT includes a semiconductor layer of amorphous silicon or polysilicon, a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode.
A TFT including a polysilicon layer usually places the gate electrode on the polysilicon layer and the polysilicon layer includes lightly doped regions disposed between a channel region and source and drain regions for reducing punch through, etc.
The heavily doped regions such as source and drain regions and the lightly doped regions are often formed by making a gate electrode include two metal films having different widths and by using the two metal films as masks for forming the two regions.
However, it is difficult to differentiate the two metal films using only one lithography step and to define the length of the lightly doped regions such that the process time is long and the productivity is decreased.
In addition, a gate insulating film disposed on the polysilicon layer requires high energy for ion implantation for forming the source and the drain regions, which in turn requires high voltage to be exerted on an implantation chamber. The high voltage of the chamber may be dangerous and may damage on the TFTs.